This disclosure relates to clock and data recovery (“CDR”) circuits, in particular having a second-order digital filter associated with the receiver of a serial data signal. The digital filter estimates the phase position of upcoming level transitions in the serial data signal, and a phase interpolator controls sampling to occur at an optimal time. The digital filter resembles a feedback control loop based on frequency and phase. According to one aspect, control latency is reduced by operating a feedback leg for phase information at a higher repetition rate than that of a parallel feedback leg for frequency information.
A plesiochronous timing configuration is defined as having no synchronizing clock signal coupling a serial data source and receiver, apart from the serial data signal itself. The transmitter encodes the serial data according to a transmitter clock signal. At the data receiver, synchronizing information is inferred from the timing of transitions that are found in the serial data signal, such as voltage or light level transitions. The timing of the data signal transitions is used to synchronize a local clock signal in the receiver with the transitions in the data.
Because the data content is arbitrary, transitions do not occur at every possible transition time. At times the data content can contain a succession of bits at an unchanging level, i.e., no transitions over plural successive data bit periods. The CDR receiver circuit has a controllable oscillator or a controllable delay that it seeks to operate to match the frequency and phase of the serial data signal. One might think that when no transitions occur in the data signal for a time, such that no information is available to update the controllable oscillator or delay in the receiver, the controllable oscillator/delay should be kept stable, at the last known frequency/phase condition of the data signal, until transitions resume. But the object advantageously is to anticipate the timing of the next transition. If the controls of the receiver clock were in the process of executing a change in frequency or phase when a hiatus in data transitions happened, it may be more effective to continue to execute that change, rather than to remain stable.
In a feedback control, each transition in the data contributes early/late information that can be applied to control the frequency/phase of the receiver clock. A second order digital filter in the feedback control has portions that respond separately to frequency and phase error. Thus the control can respond both to phase error and also to accumulating phase error. An accumulating phase error is a frequency error. The feedback control can anticipate the timing of future data level transitions. However, what are needed are circuits and techniques that optimize and improve the operation of such a control, especially by making the control highly responsive.